The invention relates to a method as recited in the preamble of claim 1. Stand-alone memory integrated circuit chips have been growing in size during many years. Large-size memories, and in particular DRAMs, suffer from low manufacturing yield. It has become common practice to provide such memory arrays with spare rows and/or columns that may be used after testing to repair a faulty array by replacing a faulty row or column, respectively. In common manufacturing practice, a 2% redundancy may triple manufacturing yield. Testing of memory arrays has become a refined art, based on presenting the array with many test stimuli with a prescribed content and in a prescribed sequence, and subsequently reading the stored content for comparison with the expected response. The combination of stimulus and expected response is sometimes called the test pattern.
Of late, processing or similar other circuitry has been combined with a large amount of so-called embedded memory. The nature of such other circuitry is not critical to the present invention, inasmuch as it may be a conventional instruction-based processor, a single-purpose digital logical circuit, circuitry for treating analog signals, and a multitude of other items. For digital processing, the setup often allows an increased communication bandwidth between logic on the one hand and memory on the other hand, than between the overall circuit and the environment, both in terms of data path width and also in terms of bit rate per wire. Similar arguments apply to situations where at least part of the operations are analog. In general, the memory to a large extent is isolated from the chip""s surroundings. Furthermore, in contradistinction with stand-alone memory arrays, the embedded array often has a much larger number of I/O bit terminals than the overall chip has available data pins. Hence, immediate access to the array is often unfeasible.
Furthermore, due to the large number of test patterns required, parallel-to-serial conversion of the complete response patterns for external verification would appreciably slow down the execution of the test. On the other hand, restricting to an inexpensive on-chip pass/fail determination, such as through a signature-generating mechanism or through a xe2x80x9chalt on first faultxe2x80x9d, would not allow to execute the repair operations.
On the other hand, providing the whole test and repair circuitry on-chip is relatively complicated and hence, expensive, inter alia because the test result should provide on-chip pointers to the various fault locations for repair. Therefore, an improved trade-off should require only moderate extensions of the on-chip facilities, while at the other hand necessitating only little communication with the external world, whilst still providing a lossless compressed response pattern.
In consequence, amongst other things, it is an object of the present invention to provide facilities for generating an abbreviated test result, based on the recognition that many tested addresses, even if faulty, will result in identical fault response patterns, and therefore would allow the use of certain compression or extraction procedures without loss of information.
Now therefore, according to one of its aspects, the invention is characterized according to the characterizing part of claim 1. The invention also relates to a memory-based device being arranged for implementing a method as claimed in claim 1. Further advantageous aspects of the invention are recited in dependent Claims.